superscalar An architectural approach for high-performance computation where a number of instructions are simultaneously accessed from memory and, where data dependency constraints allow, are issued for simultaneous execution by multiple independent pipelines, thus giving an enhanced instruction execution rate. RISC processors employing multiple-issue superscalar pipelines are currently available. Optimized compilation is needed to minimize data dependencies between consecutive instructions in order to maximize multiple-issue opportunities and hence performance. See also VLIW.
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