Compiler Attempts To Address The Timing Closure Challenge.(Synopsys Physical Compiler)(Product Announcement)

From: Electronic Design | Date: January 24, 2000| Author: | Copyright information

Achieving timing closure with today's complex IC designs is quite a challenge. In fact, it may be one of the most daunting tasks designers are faced with. While a number of solutions to this problem have emerged, none has managed to garner widespread industry approval. Synopsys, however, has entered the fray with a tool that promises to help designers meet timing closure and get the best possible performance out of their designs at the same time.

This new tool, Physical Compiler, specifically targets both front-end and back-end designers. It works by allowing ...

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